Asynchronous sample rate conversion between the ho

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Asynchronous sampling rate conversion between AES audio data streams

the wide use and continuous innovation of digital video and audio technology have promoted the rapid development of audio/video broadcasting (AVB) equipment. Today's AVB devices need higher image quality, resolution, higher bandwidth and more audio/video processing channels, and need to combine previously independent but actually interrelated functions (such as HD-SDI, audio multiplexing and demultiplexing, and asynchronous sample rate conversion (ASRC))

xilinx FPGA meets the extensive needs of customers for integrated tensile testing machines by constantly combining the functions of low integration, complex and expensive ASSP chips. Use chip features such as dsp48e and block ram to realize complex filtering functions. As a function realized by ASSP chip, ASRC can be integrated into Xilinx FPGA

similarly, the Xilinx Application guide and reference design provided free of charge can also meet customers' needs for integrating complex algorithms to realize computer control, data processing, display and other functions. The ASRC reference design correctly handles synchronous sample rate conversion and the more complex ASRC required by most audio/video products

many ASSP chip and FPGA IP providers provide a relatively simple method of only using synchronization, and the resource utilization of each audio channel is small; However, when applied to asynchronous applications, these methods will produce the following problems:

the accumulation of delay leads to the change of input-output delay

noise will be generated in audio, such as missed sampling or repeated sampling, both of which show unwanted distortion

understanding sampling rate conversion

before understanding the theory of digital sampling rate conversion, let's take a look at the basic problems that audio/video engineers are trying to solve. In a few applications, synchronous conversion with fixed rate can be used, such as using the same clock source or the output clock generated by the input clock to convert 48Khz input to 44.1KHz output. However, it is more likely that asynchronous conversion occurs, and the input and output clocks are completely independent, such as audio communication between two circuit boards. Different clock oscillators can have the same nominal frequency, but there is a few parts per million difference. Xilinx ASRC reference design provides two important and difficult design functions for asynchronous applications with independent input and output clocks:

automatically and accurately monitor the ratio of input to output sampling rate and the change of sampling rate

dynamically adjust the filter function (filter coefficient) to maximize performance

use FPGA to support digital audio ASRC, It means that the cost of each SDI interface in the system can be greatly reduced, and in many systems, there are many channels

xilinx ASRC IP has high performance, and its worst-case input-output signal-to-noise ratio is? 125dB。 It can also support the conversion from multiple audio input frequencies to multiple audio output frequencies. The sampling rate conversion algorithm can be dynamically adjusted to maintain the highest performance, so that designers do not need to pay special attention to the input and output clocks. All these functions can be verified using the IP running on the Xilinx ml571 serial digital video demo board as shown in Figure 1. Moreover, these extensive functions and high-performance ASRC IP are free

Figure 1 ml571 board and frame synchronization demonstration board use ASRC to match the output digital audio sampling rate and the output digital video sampling rate sampling rate conversion theory

Figure 2 shows the concept of up conversion or down conversion under normal circumstances. The frequency conversion ratio can change continuously within the range of rational numbers with decimals

Figure 2 classic data concept for sampling rate conversion

it can be seen from the block diagram that the up conversion (to generate more samples and time positions for selection) is carried out first, and then the down conversion (to select the sample in the output data stream that is most consistent with the desired sample position). The anti-interference/anti aliasing filter in the data path ensures that the spectral range is less than half of the Nyquist rate of the input and output sampling frequencies. Figures 3 and 4 show that for each output sampling position or output phase, a different set of sub filter coefficients is required, because the input is in different positions relative to the output phase. A sub filter with a set of coefficients corresponding to the input sampling position is realized by interpolating the prototype filter coefficients. When the sub filter is convoluted with the corresponding input samples, the required output samples will be generated. This process will be repeated continuously, inserting new sub filter coefficients for each output sample

the sample position related to the original sample position in Figure 3 shows the interpolation sample used

Figure 4 the prototype filter located in the center of the output sample position

the example of implementing ASRC on ml571

is called a simple function of video frame synchronization, which well shows the main purpose of ASRC. Video signals can be stored in the frame buffer at a certain rate and taken out at a slightly different rate. If the two parts of the video device are not locked in phase synchronously and work at different pixel rates, this process will be very useful. Here is a simple explanation for you from Shandong Sida high tech

the result is that occasionally a frame of video data needs to be added or discarded. The human eye may not notice the video frames added or discarded on the TV screen, but the human ear can well detect similar differences in audio. The solution is to remove the audio data from the initial video data stream, and then insert it into the data stream with small data rate changes, and make the sampling rate of the output audio match the sampling rate of the new output video. Xilinx ASRC reference design is very suitable for such a task

for example, let's connect two boards with slightly different SDI video sampling rates caused by different clock oscillators. The receiving board separates the embedded AES digital audio signal from the video stream and sends it to ASRC. We need to use frame cache synchronization logic to deal with the clock frequency difference between the two boards by adding or discarding video frames. ASRC adjusts the de embedded audio to match the time limited isochronous rate of the output video stream so that it can be re embedded into the output SDI video stream. (it is necessary to use the frame cache synchronization logic to deal with the clock frequency difference between the two boards by adding or discarding video frames. ASRC adjusts the de embedded audio to match the clock rate of the output video stream so that it can be re embedded into the output SDI video stream.)

block diagram and performance advantages

the simple block diagram in Figure 5 shows two key design parts that are necessary in ASRC. The first part is used to determine the change between the input sampling rate and the output sampling rate, which is marked with proportional control. The second part of the secondary sampler is a group of prototype filters, which change according to the statistical data provided by proportional control

Figure 5 top level block diagram of xilinxasrc reference design

asrc reference design converts stereo audio from one sampling frequency to another. The input and output frequencies can be in any proportion to each other, or the same frequency based on different clocks. The output is the bandwidth limited version of the input, and the input is resampled to match the output sampling timing. The reference design has the following characteristics:

fully asynchronous operation

expandable to multiple channels

worst case -125db thd+n, typical case -130db thd+n

input and output of 24 bit audio word width, 31 bit internal mathematical accuracy and carry away from 0

automatically monitor the ratio of input to output sampling rate, and constantly adjust the filter

continuous rational/decimal ratio, Up conversion is 8:1

continuous rational/decimal ratio, down conversion is 1:7.5

continuous input to output sampling rate monitoring with adaptive filtering function

input/output sampling rate is in the continuous range of 8khx-192khz

lower deterministic delay

reference design FIR filter with an interpolation coefficient, It is implemented by dsp48e as the main mathematical unit in virtex TM -5 and block RAM as input sampling cache and prototype storage


maintaining different input to output audio sampling rates for different numbers of digital audio channels and supporting the need for new AVB functions is a huge challenge. From the aspects of changing protocols, memory management, different loads and different system interfaces, it is easy to see that these designs need high-performance and low-cost flexibility that ASSP and ASIC cannot provide. These challenges create opportunities for Virtex-5 devices, because these devices enable equipment manufacturers to create corresponding solutions for the growing AVB equipment market

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